Phase-Locked Loop (PLL)
A PLL is a negative feedback system where an oscillator-generated signal is phase and frequency locked to a reference signal.
Typical applications of PLL are:
- Frequency Synthesis (e.g. generating a 1 GHz clock from a 50 MHz reference)
- Clock Deskewing (e.g. phase-aligning an internal clock to an output clock to external device)
- Extracting a clock from a random data stream (e.g. serial-link receiver)
The basic building block of PLL are:
- Phase Detector
- Loop Filter
- Voltage-Controlled Oscillator
The basic operation of PLL can be divided into 3 steps.
1. The phase detector catches the phase difference between its two inputs and generates an output error signal Ve whose average value is linearly proportional to the phase difference.
- Example: Depending on the application of the PLL, different kind of phase detectors can be implemented each with its pros and cons. In this example we will use one of the simplest form of phase detectors – XOR gate.
2. A loop filter is then used to suppress the high frequency components of the phase detector output(Ve) allowing the average value (Vctrl) to control the VCO frequency.
3. Voltage Controlled Oscillator generates an output signal (CLK_FB) whose frequency is a linear function of the control signal out of the loop filter.
Delay-Locked Loop (DLL)
The DLL is used for phase syncronisation of a reference clock with a system clock. Both the reference clock (CLK_IN) and the system clock (CLK_OUT) have the same frequency. Using a controllable delay line the DLL delays the reference clock until its phase is aligned with the system clock. The Delay Locked Loop (DLL) typically do not multiply an input clock (contrary to the PLL), although high performance DLLs have been designed to implement limited frequency multiplication. DLLs are also inherently stable.
Typical applications of DLL are:
- Clock Deskewing (Delay Compensation)
- Multiphase Clock Generation
- Frequency Synthesis (Very limited compared to PLL)
- Clock & Data Recovery Systems