Microcontrollers use pins for interfacing with the outside world. In general, the pins are the physical points on the package of an integrated circuit (IC) where a connection can be made to the printed circuit board. Behind each pin (inside the IC) there is a special circuitry used for driving it. This circuitry (usually called a pad) can be configured to allow the pin to interface with different types of digital and analog circuits. Choosing the proper pin configuration is an important part of designing an embedded system. In this article, we will cover the most common types of output configurations and their applications.
In order to explain the specifics of each output configuration, we must first introduce the following terms:
High impedance (High-Z, Hi-Z) pin -A pin that is characterized by having a high impedance which effectively removes its influence on the electrical circuit it is connected to. It is not actively driven and is “floating” unless another external device or circuitry (pull-up/pull-down) is driving it.
Floating pin – A pin is “floating” if it is left unconnected and is also not driven by a circuit inside the integrated circuit. Its voltage level is undefined and unpredictable. A high impedance pin that is not driven by a pull-up or pull-down circuit is said to be floating.
Pull-up and pull-down resistors – These resistors are used to set a specific level (logic 0 or logic 1) at a floating pin. A pull-up resistor is connected to the power supply so it can pull the floating pin to logic high level. A pull-down resistor connects the floating pin to the ground (logic 0).
Push-Pull
Push-pull is the most common output configuration. Just as its name suggests,
In Fig. 1 we can see a push-pull output implementation using a PMOS and an NMOS transistor. Shown on the left side is the operation during the push phase and on the right side is the operation during the pull phase.
- Push phase – When the Internal Signal connected to the gates of the transistors (see the figure above) is set to a low logic level (logic 0), the PMOS transistor is activated and current flows through it from the VDD to the output pin. NMOS transistor is inactive (open) and not conducting.
- Pull phase – When the Internal Signal connected to the gates of the transistors is set to a high logic level (logic 1), the NMOS transistor is activated (closed) and current starts to flow through it from the output pin to the GND. At the same time, the PMOS transistor is inactive (open) and is not conducting current.
This type of output doesn’t allow connecting multiple devices together in a bus configuration, like the open drain output. Push-pull configuration is most commonly used in interfaces that have unidirectional lines (transmission on the line is only in a single direction – SPI, UART etc.).
As push-pull outputs are constantly driven (high or low), they provide better performance when it comes to the slopes of the generated output digital signals.
It should be noted that an output pin configured as push-pull can in most cases be dynamically reconfigured to become an input. This is achieved by closing both of the transistors, thus achieving high impedance state on the line. Then the line can be driven from other external devices and sensed with dedicated logic inside the integrated circuit.
Open Drain
In
On Fig. 2 we can see an open drain output. It is implemented using an N-channel MOS transistor that pulls the output pin to ground when the transistor is on and leaves it floating when the transistor is off.
Open drain outputs are most commonly used in communication interfaces where multiple devices are connected on the same line (e.g I2C, One-Wire etc.). When all of the outputs of the devices connected to the line are in Hi-Z state, the line is driven to a default logic 1 level by a pull-up. Any device can pull the line to logic 0 using its open drain output and all devices can see this level.
There are few things that have to be considered when using a pull-up resistor with the open drain output configuration
Rising edge slope – The pull-up resistor in combination with the inherent capacitance of the line forms a low-pass filter. Depending on the value of the resistor and the capacitance of the line there can be a visible difference in the slopes of the rising edges compared to the falling edges. The falling edge is sharper as it is achieved using the transistor which has very low internal resistance. The rising edge, however, is formed by the pull-up resistor and the aforementioned low-pass filtering effect is more pronounced.
Power consumption and noise interference – A trade-off exists when choosing the value of the pull-up resistors. When a device on the line drives logic 0
Summary
Push-pull output is best suited for communication interfaces that have single direction lines (e.g SPI, UART etc.).Open drain is commonly used for bidirectional single line communication interfaces, where more than two devices are connected on the same line(e.g I2C, One-Wire etc.)- Open drain output has higher power consumption during active transfers due to the pull-up resistors that are used.
- In general, the push-pull output has faster slopes than the open drain output.
Figure 2 is not a NMOS. That is a PMOS and using a wrong schematic for N channel MOSFET makes more confusion for newbies.
Hello,
There are a lot of symbol variations for MOSFET transistors. This can cause confusion sometimes.
The transistor shown in Figure 2 is NMOS using the following symbol https://en.wikipedia.org/wiki/MOSFET#/media/File:Mosfet_N-Ch_Sedra.svg.
Any reason for the presented configuration of the push-pull circuit?(Why the PMOS transistor is connected to VCC and not to ground and viceversa)…It has anything to do with the fact the open drain circuit has a NMOS connected to ground(so that NMOS can be used as a half of the push-pull without any modifications )?
Hello Andrei,
The presented push-pull configuration (with PMOS being the top switch and connected to VCC) is the most common one. You are correct that this push-pull can also act as a pure open-drain configuration without any modification (aside from additional logic for controlling the PMOS gate individually). All microcontrollers with outputs that can be configured as push-pull and open-drain use this approach. Additionally, you can look at the differences between NMOS and PMOS when it comes to passing Low-level and High-level signals: https://www.quora.com/Why-is-PMOS-good-to-pass-logic-1-and-NMOS-is-good-to-pass-logic-0.
Is it Ok to tie / Combine Open Drain output to a Push Pull to drive a logic
Not sure where this scenario is needed. Can you provide a little bit more information? The setup you describe can cause shorts in some cases.
Doubt in the figure, the representation of PMOS and NMOS
somebody please present a MOSFET Push Pull drive(<10mA) for a clock signal of 3.3V and 5V amplitude
very good explanation, much appreciated