The arithmetic logic unit (ALU) is at the hearth of the microprocessor. It is designed to perform both arithmetic and logical operations on integer binary numbers.

### Principle of operation

The ALU does not need a clock signal as it is a pure combinational digital circuit. The output will change asynchronously in response to change on the inputs (called operands). Fig. 1 ALU

The ALU performs two categories of operations:

1. Arithmetic operations:
• Subtraction
• Shift Left
• Shift Right
2. Logic operations:
• AND
• OR
• Shift Left
• Shift Right

The operation to be carried out by the ALU is selected by a control line, shown on Fig.1 as Opcode.

Multiplication and division are usually not part of the arithmetic operations that the ALU can perform. As they are considerably more complicated operations and thus requiring more complicated hardware, they are implemented as separate units inside the CPU. The ALU however can be used for certain types of division and multiplication using arithmetic shift operations (see our article for additional information Logical vs. Arithmetic Shift).

### Status Flags

The ALU provides a feedback on the outcome of the operations it performs using a special bits called status flags. . The most common status flags are the following:

• Zero flag – indicates that the result of the ALU operation is zero (0).
• Negative flag – indicates that the MSB of the output result is 1. As the ALU itself does not differentiate between unsigned integers and 2’s complement signed integers, this flag is used for 2’s complement interpretation outside of the ALU logic.
• Carry flag – indicates that there is a carry from the addition operation.
• Overflow flag – This flag indicates an overflow during the ALU operation (for additional information see our article Overflow in Digital Systems). It can be used for result interpretation when we work with 2’s complement representation. It has the following behavior:
• Set to 1 when MSB of input A is 1, MSB of input B is also 1, but the MSB of the output is 0
• Set to 1 when MSB of input A is 0, MSB of input B is also 0, but the MSB of the output is 1
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