Instruction Set Architecture (ISA) specifies the instructions that a microprocessor can execute. It can be viewed as a programmer’s manual. It clearly defines everything needed for writing either a compiler or machine language program for a microprocessor supporting particular ISA. The ISA itself does not contain hardware implementations details. There can be microprocessors with different microarchitectures supporting the same ISA.
The instruction set architecture specifies:
- Memory organisation – the total addressable memory locations, the size of each address
- Data types
- General purpose registers
- Addressing modes
- Instruction set (machine language) – size of instructions (length), instruction formats etc.
Popular ISA today are:
- Power PC
- RISC V
Most of the ISA require a license in order to be used. There are also open-source ISAs (e.g RISC V)
– Accumulator based
This architectures uses only one explicit operand per instruction. The second operand, if it is required is a special register called the accumulator (implicit). Almost all of the CPU instructions use the accumulator, although there may be additional special CPU registers.
LOAD A ; Load the value of memory cell A into the аaccumulator
ADD B ; Add the value of memory Cell B to the accumulator value
STORE C; Store the value of the accumulator in memory cell C
Typically there are only two operands. Both operands are explicit. One operand is a memory cell, the other is a CPU register.
MOV r1, A ; Store the value of memory cell A into register r1
ADD r1, B ; Add the value of memory Cell B into register r1
MOV C, r1 ; Store the value of register r1 into memory cell C
– Load/Store (register-register)
The operands are CPU registers. Access to the memory is available only through LOAD and STORE instructions.
LD r1, A ; Load the value of memory cell A into register r1
LD r2, B ; Load the value of memory cell B into register r2
ADD r3, r1, r2 ; Add the contents of register r1 with register r2 and store the result in r3
ST C, r3 ; Store the value of register r3 in memory cell C
– Von-Neumann architecture
In this architecture there is only one memory bus that is used for both data transfers and instruction fetching.
– Harvard architecture
In this architecture there are two separate memory buses. One is used for data transfers and the other one for instruction fetching. This allows those operation to be performed simultaneously.
Complexity of Instructions
– RISC (Reduced Instruction Set Computing)
- relatively small number of simple instructions
- most instructions have the same execution time (CPU clock cycles)
- enables pipelining
- fixed instruction length
- few instruction formats
- load/store architecture
- requires complex compiler
– CISC (Complex Instruction Set Computing)
- one instruction can perform many low-level operations
- most instructions are executed within multiple clock cycles
- simpler compilers