Clock skew exists in every synchronous system. The edge of the system clock arrives at different times at different points in the system. This difference in arrival times is defined as clock skew.
Few facts about clock skew:
- It’s caused by different path delays to different points in the design.
- It’s is constant from cycle to cycle
- It does not change the period of the clock signal
If the clock skew is large it can potentially cause:
- timing violations
- functional failures
Example: Two flip-flops clocked by the same clock.The output of the first one is connected to the input of the second one. If the clock skew is larger than the data propagation delay between the two flip-flops this can cause what is usually referred to as a Short path problem.
Add figure showing the effects of clock skew!
since the same clock edge arrives at the second flip-flop later than the new data, the second flip-flop output switches at the same edge as the first flip-flop and with the same data as the first flip-flop.
Removing Clock Skew (Deskewing)
Completely removing the clock skew is not possible, the goal is to minimize it to a negligible small value or a value that is tolerable by the system.
The system clock propagated thru the system (to unit B inside the FPGA and unit C external to the FPGA) will have a skew. It will be bigger at Unit C due to the longer path the system clock has to travel (See Fig.3)
Removing the clock skew in the system described above can be achieved using Phase Locked Loops or Delay Locked Loops. For example two DLL can be used – one for deskewing CLK_B and one for deskewing CLK_C (See Fig. 4).
Let’s analyze for Unit B:
The DLL will try to align it’s output to its reference input. In this case the reference input is the System Clock (CLK_SYS) and the feedback is taken directly from CLK_B input of Unit B. So the task of the DLL is to align CLK_SYS with CLK_B. If we look back at Fig. 3 we can see the skew on CLK_B. In order to compensate the path delay, the DLL should output (DLL_B) version of its input signal (SYS_CLK) that is ahead of it and of course the DLL has no predicton capabilities. Instead the output DLL_B is delayed enough so that it appears as it’s ahead of the SYS_CLK with the exact same value CLK_B is behind SYS_CLK. This in turn removes(minimizes) the clock skew.